diff --git a/post/cpu/ppc4xx/cache.c b/post/cpu/ppc4xx/cache.c
index be6a2bf..482f819 100644
--- a/post/cpu/ppc4xx/cache.c
+++ b/post/cpu/ppc4xx/cache.c
@@ -33,7 +33,7 @@
 
 #include <post.h>
 
-#if CONFIG_POST & CFG_POST_CACHE
+#if CONFIG_POST & CONFIG_SYS_POST_CACHE
 
 #include <asm/mmu.h>
 #include <watchdog.h>
@@ -54,7 +54,7 @@
 
 int cache_post_test (int flags)
 {
-	void *virt = (void *)CFG_POST_CACHE_ADDR;
+	void *virt = (void *)CONFIG_SYS_POST_CACHE_ADDR;
 	int ints;
 	int res = 0;
 	int tlb = -1;		/* index to the victim TLB entry */
@@ -119,4 +119,4 @@
 	return res;
 }
 
-#endif /* CONFIG_POST & CFG_POST_CACHE */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */
diff --git a/post/cpu/ppc4xx/cache_4xx.S b/post/cpu/ppc4xx/cache_4xx.S
index 455ffa0..3f3e585 100644
--- a/post/cpu/ppc4xx/cache_4xx.S
+++ b/post/cpu/ppc4xx/cache_4xx.S
@@ -31,7 +31,7 @@
 #include <asm/cache.h>
 #include <asm/mmu.h>
 
-#if CONFIG_POST & CFG_POST_CACHE
+#if CONFIG_POST & CONFIG_SYS_POST_CACHE
 
 	.text
 
@@ -115,8 +115,8 @@
  */
 cache_post_dinvalidate:
 	dcbi	r0, r3
-	addi	r3, r3, CFG_CACHELINE_SIZE
-	subic.	r4, r4, CFG_CACHELINE_SIZE
+	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE
+	subic.	r4, r4, CONFIG_SYS_CACHELINE_SIZE
 	bgt	cache_post_dinvalidate
 	sync
 	blr
@@ -125,8 +125,8 @@
  */
 cache_post_dstore:
 	dcbst	r0, r3
-	addi	r3, r3, CFG_CACHELINE_SIZE
-	subic.	r4, r4, CFG_CACHELINE_SIZE
+	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE
+	subic.	r4, r4, CONFIG_SYS_CACHELINE_SIZE
 	bgt	cache_post_dstore
 	sync
 	blr
@@ -135,8 +135,8 @@
  */
 cache_post_dtouch:
 	dcbt	r0, r3
-	addi	r3, r3, CFG_CACHELINE_SIZE
-	subic.	r4, r4, CFG_CACHELINE_SIZE
+	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE
+	subic.	r4, r4, CONFIG_SYS_CACHELINE_SIZE
 	bgt	cache_post_dtouch
 	sync
 	blr
@@ -486,4 +486,4 @@
 	li	r3, -1
 	blr
 
-#endif /* CONFIG_POST & CFG_POST_CACHE */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */
diff --git a/post/cpu/ppc4xx/denali_ecc.c b/post/cpu/ppc4xx/denali_ecc.c
index 12a1bbf..6ab1593 100644
--- a/post/cpu/ppc4xx/denali_ecc.c
+++ b/post/cpu/ppc4xx/denali_ecc.c
@@ -35,7 +35,7 @@
 
 #include <post.h>
 
-#if CONFIG_POST & CFG_POST_ECC
+#if CONFIG_POST & CONFIG_SYS_POST_ECC
 
 /*
  * MEMORY ECC test
@@ -267,5 +267,5 @@
 	debug("ecc_post_test() returning %d\n", ret);
 	return ret;
 }
-#endif /* CONFIG_POST & CFG_POST_ECC */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_ECC */
 #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c
index ccbfcf9..e40e19b 100644
--- a/post/cpu/ppc4xx/ether.c
+++ b/post/cpu/ppc4xx/ether.c
@@ -39,7 +39,7 @@
 
 #include <post.h>
 
-#if CONFIG_POST & CFG_POST_ETHER
+#if CONFIG_POST & CONFIG_SYS_POST_ETHER
 
 #include <asm/cache.h>
 #include <asm/io.h>
@@ -209,7 +209,7 @@
 	mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum));
 
 	/* set internal loopback mode */
-#ifdef CFG_POST_ETHER_EXT_LOOPBACK
+#ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
 	out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | 0 |
 		  EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
 		  EMAC_M1_MF_100MBPS | EMAC_M1_IST |
@@ -406,8 +406,8 @@
 	int i;
 
 	/* Allocate tx & rx packet buffers */
-	tx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
-	rx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
+	tx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
+	rx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
 
 	if (!tx_buf || !rx_buf) {
 		printf ("Failed to allocate packet buffers\n");
@@ -427,4 +427,4 @@
 	return res;
 }
 
-#endif /* CONFIG_POST & CFG_POST_ETHER */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */
diff --git a/post/cpu/ppc4xx/ocm.c b/post/cpu/ppc4xx/ocm.c
index 88aa93e..584e30c 100644
--- a/post/cpu/ppc4xx/ocm.c
+++ b/post/cpu/ppc4xx/ocm.c
@@ -38,19 +38,19 @@
 #define OCM_TEST_PATTERN1	0x55555555
 #define OCM_TEST_PATTERN2	0xAAAAAAAA
 
-#if CONFIG_POST & CFG_POST_OCM
+#if CONFIG_POST & CONFIG_SYS_POST_OCM
 
 static uint ocm_status_read(void)
 {
-	return in_be32((void *)CFG_OCM_STATUS_ADDR) &
-		CFG_OCM_STATUS_MASK;
+	return in_be32((void *)CONFIG_SYS_OCM_STATUS_ADDR) &
+		CONFIG_SYS_OCM_STATUS_MASK;
 }
 
 static void ocm_status_write(uint value)
 {
-	out_be32((void *)CFG_OCM_STATUS_ADDR, value |
-		(in_be32((void *)CFG_OCM_STATUS_ADDR) &
-			~CFG_OCM_STATUS_MASK));
+	out_be32((void *)CONFIG_SYS_OCM_STATUS_ADDR, value |
+		(in_be32((void *)CONFIG_SYS_OCM_STATUS_ADDR) &
+			~CONFIG_SYS_OCM_STATUS_MASK));
 }
 
 static inline int ocm_test_word(uint value, uint *address)
@@ -68,11 +68,11 @@
 {
 	uint   old_value;
 	int    ret = 0;
-	uint  *address = (uint*)CFG_OCM_BASE;
+	uint  *address = (uint*)CONFIG_SYS_OCM_BASE;
 
-	if (ocm_status_read() == CFG_OCM_STATUS_OK)
+	if (ocm_status_read() == CONFIG_SYS_OCM_STATUS_OK)
 		return 0;
-	for (; address < (uint*)(CFG_OCM_BASE + CFG_OCM_SIZE); address++) {
+	for (; address < (uint*)(CONFIG_SYS_OCM_BASE + CONFIG_SYS_OCM_SIZE); address++) {
 		old_value = *address;
 		if (ocm_test_word(OCM_TEST_PATTERN1, address) ||
 				ocm_test_word(OCM_TEST_PATTERN2, address)) {
@@ -83,7 +83,7 @@
 		}
 		*address = old_value;
 	}
-	ocm_status_write(ret ? CFG_OCM_STATUS_FAIL : CFG_OCM_STATUS_OK);
+	ocm_status_write(ret ? CONFIG_SYS_OCM_STATUS_FAIL : CONFIG_SYS_OCM_STATUS_OK);
 	return ret;
 }
-#endif /* CONFIG_POST & CFG_POST_OCM */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_OCM */
diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c
index 110df6e..ecb87b5 100644
--- a/post/cpu/ppc4xx/spr.c
+++ b/post/cpu/ppc4xx/spr.c
@@ -37,7 +37,7 @@
 
 #include <post.h>
 
-#if CONFIG_POST & CFG_POST_SPR
+#if CONFIG_POST & CONFIG_SYS_POST_SPR
 
 #include <asm/processor.h>
 
@@ -198,4 +198,4 @@
 	return ret;
 }
 
-#endif /* CONFIG_POST & CFG_POST_SPR */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_SPR */
diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c
index 1a57c3d..84a4d0a 100644
--- a/post/cpu/ppc4xx/uart.c
+++ b/post/cpu/ppc4xx/uart.c
@@ -34,14 +34,14 @@
 
 #include <post.h>
 
-#if CONFIG_POST & CFG_POST_UART
+#if CONFIG_POST & CONFIG_SYS_POST_UART
 
 /*
  * This table defines the UART's that should be tested and can
  * be overridden in the board config file
  */
-#ifndef CFG_POST_UART_TABLE
-#define CFG_POST_UART_TABLE	{UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE}
+#ifndef CONFIG_SYS_POST_UART_TABLE
+#define CONFIG_SYS_POST_UART_TABLE	{UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE}
 #endif
 
 #include <asm/processor.h>
@@ -50,17 +50,17 @@
 #if defined(CONFIG_440)
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-#define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000300
-#define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000400
-#define UART2_BASE  CFG_PERIPHERAL_BASE + 0x00000500
-#define UART3_BASE  CFG_PERIPHERAL_BASE + 0x00000600
+#define UART0_BASE  CONFIG_SYS_PERIPHERAL_BASE + 0x00000300
+#define UART1_BASE  CONFIG_SYS_PERIPHERAL_BASE + 0x00000400
+#define UART2_BASE  CONFIG_SYS_PERIPHERAL_BASE + 0x00000500
+#define UART3_BASE  CONFIG_SYS_PERIPHERAL_BASE + 0x00000600
 #else
-#define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000200
-#define UART1_BASE  CFG_PERIPHERAL_BASE + 0x00000300
+#define UART0_BASE  CONFIG_SYS_PERIPHERAL_BASE + 0x00000200
+#define UART1_BASE  CONFIG_SYS_PERIPHERAL_BASE + 0x00000300
 #endif
 
 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
-#define UART2_BASE  CFG_PERIPHERAL_BASE + 0x00000600
+#define UART2_BASE  CONFIG_SYS_PERIPHERAL_BASE + 0x00000600
 #endif
 
 #if defined(CONFIG_440GP)
@@ -147,7 +147,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_440) || defined(CONFIG_405EX)
-#if !defined(CFG_EXT_SERIAL_CLOCK)
+#if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
 static void serial_divs (int baudrate, unsigned long *pudiv,
 			 unsigned short *pbdiv)
 {
@@ -196,7 +196,7 @@
 	unsigned long udiv;
 	unsigned short bdiv;
 	volatile char val;
-#ifdef CFG_EXT_SERIAL_CLOCK
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 	unsigned long tmp;
 #endif
 	int i;
@@ -209,11 +209,11 @@
 	MFREG(UART0_SDR, reg);
 	reg &= ~CR0_MASK;
 
-#ifdef CFG_EXT_SERIAL_CLOCK
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
 	reg |= CR0_EXTCLK_ENA;
 	udiv = 1;
 	tmp  = gd->baudrate * 16;
-	bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
+	bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp;
 #else
 	/* For 440, the cpu clock is on divider chain A, UART on divider
 	 * chain B ... so cpu clock is irrelevant. Get the "optimized"
@@ -278,7 +278,7 @@
 #ifdef CONFIG_405EP
 	reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
 	clk = gd->cpu_clk;
-	tmp = CFG_BASE_BAUD * 16;
+	tmp = CONFIG_SYS_BASE_BAUD * 16;
 	udiv = (clk + tmp / 2) / tmp;
 	if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
 		udiv = UDIV_MAX;
@@ -287,16 +287,16 @@
 	mtdcr (cpc0_ucr, reg);
 #else /* CONFIG_405EP */
 	reg = mfdcr(cntrl0) & ~CR0_MASK;
-#ifdef CFG_EXT_SERIAL_CLOCK
-	clk = CFG_EXT_SERIAL_CLOCK;
+#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
+	clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
 	udiv = 1;
 	reg |= CR0_EXTCLK_ENA;
 #else
 	clk = gd->cpu_clk;
-#ifdef CFG_405_UART_ERRATA_59
+#ifdef CONFIG_SYS_405_UART_ERRATA_59
 	udiv = 31;			/* Errata 59: stuck at 31 */
 #else
-	tmp = CFG_BASE_BAUD * 16;
+	tmp = CONFIG_SYS_BASE_BAUD * 16;
 	udiv = (clk + tmp / 2) / tmp;
 	if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
 		udiv = UDIV_MAX;
@@ -375,7 +375,7 @@
 int uart_post_test (int flags)
 {
 	int i, res = 0;
-	static unsigned long base[] = CFG_POST_UART_TABLE;
+	static unsigned long base[] = CONFIG_SYS_POST_UART_TABLE;
 
 	for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) {
 		if (test_ctlr (base[i], i))
@@ -386,4 +386,4 @@
 	return res;
 }
 
-#endif /* CONFIG_POST & CFG_POST_UART */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_UART */
diff --git a/post/cpu/ppc4xx/watchdog.c b/post/cpu/ppc4xx/watchdog.c
index 7fdecb4..221adfc 100644
--- a/post/cpu/ppc4xx/watchdog.c
+++ b/post/cpu/ppc4xx/watchdog.c
@@ -37,7 +37,7 @@
 
 #include <post.h>
 
-#if CONFIG_POST & CFG_POST_WATCHDOG
+#if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG
 
 #include <watchdog.h>
 
@@ -65,4 +65,4 @@
 	}
 }
 
-#endif /* CONFIG_POST & CFG_POST_WATCHDOG */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_WATCHDOG */